ninharp/ninlight-w600
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fix: Flash-Lock im SDK, Store-Lock, Flush vor Reboot

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This commit is contained in:
Michael Sauer
2026-09-11 22:10:28 +02:00
parent dce9ad2946
commit 0648b3a252
5 changed files with 82 additions and 7 deletions
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sdk/Platform/Drivers/internalflash/wm_internal_fls.c
+18
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@@ -19,6 +19,12 @@
#include "wm_gpio.h"
#include "wm_io.h"
/* ninlight patch 5: the >1 MB (second flash) path switches the SPI pins without any lock;
* serialise it for all callers (SDK params, fwup, ninlight). See sdk/PATCHES.md. */
static tls_os_sem_t *s_fls2_lock = NULL;
#define FLS2_LOCK() do { if (s_fls2_lock) tls_os_sem_acquire(s_fls2_lock, 0); } while (0)
#define FLS2_UNLOCK() do { if (s_fls2_lock) tls_os_sem_release(s_fls2_lock); } while (0)
void tls_spifls_cs_switch(enum tls_io_name flashcs, int openflag);
void tls_spifls_di_switch(enum tls_io_name flashdi, int openflag);
void tls_spifls_do_switch(enum tls_io_name flashdo, int openflag);
@@ -611,6 +617,7 @@ int tls_fls_read(u32 addr, u8 *buf, u32 len)
{
lenfor2M = len - lenfor1M;
lenfor2M = (addrfor2M + lenfor2M) <= (FLASH_BASE_ADDR | flashtotalsize) ? lenfor2M : ((FLASH_BASE_ADDR | flashtotalsize) - addrfor2M);
FLS2_LOCK();
tls_spifls_cs_switch(WM_IO_PA_02, 1);
tls_spifls_ck_switch(WM_IO_PA_11, 1);
tls_spifls_di_switch(WM_IO_PA_03, 1);
@@ -620,6 +627,7 @@ int tls_fls_read(u32 addr, u8 *buf, u32 len)
tls_spifls_do_switch(WM_IO_PA_09, 0);
tls_spifls_ck_switch(WM_IO_PA_11, 0);
tls_spifls_cs_switch(WM_IO_PA_02, 0);
FLS2_UNLOCK();
return err;
}
@@ -756,6 +764,7 @@ int tls_fls_write(u32 addr, u8 *buf, u32 len)
{
lenfor2M = len - lenfor1M;
lenfor2M = (addrfor2M + lenfor2M) <= (FLASH_BASE_ADDR | flashtotalsize) ? lenfor2M : ((FLASH_BASE_ADDR | flashtotalsize) - addrfor2M);
FLS2_LOCK();
tls_spifls_cs_switch(WM_IO_PA_02, 1);
tls_spifls_ck_switch(WM_IO_PA_11, 1);
tls_spifls_di_switch(WM_IO_PA_03, 1);
@@ -765,6 +774,7 @@ int tls_fls_write(u32 addr, u8 *buf, u32 len)
tls_spifls_do_switch(WM_IO_PA_09, 0);
tls_spifls_ck_switch(WM_IO_PA_11, 0);
tls_spifls_cs_switch(WM_IO_PA_02, 0);
FLS2_UNLOCK();
return err;
@@ -805,6 +815,7 @@ int tls_fls_erase(u32 sector)
}
else if (sector < (flashtotalsize / INSIDE_FLS_SECTOR_SIZE + INSIDE_FLS_BASE_ADDR / INSIDE_FLS_SECTOR_SIZE))
{
FLS2_LOCK();
tls_spifls_cs_switch(WM_IO_PA_02, 1);
tls_spifls_ck_switch(WM_IO_PA_11, 1);
tls_spifls_di_switch(WM_IO_PA_03, 1);
@@ -814,6 +825,7 @@ int tls_fls_erase(u32 sector)
tls_spifls_do_switch(WM_IO_PA_09, 0);
tls_spifls_ck_switch(WM_IO_PA_11, 0);
tls_spifls_cs_switch(WM_IO_PA_02, 0);
FLS2_UNLOCK();
return err;
}
@@ -854,6 +866,7 @@ static void tls_fls_flush_sector(void)
else if (gsSector < (flashtotalsize / INSIDE_FLS_SECTOR_SIZE + INSIDE_FLS_BASE_ADDR / INSIDE_FLS_SECTOR_SIZE))
{
addr = gsSector * INSIDE_FLS_SECTOR_SIZE;
FLS2_LOCK();
tls_spifls_cs_switch(WM_IO_PA_02, 1);
tls_spifls_ck_switch(WM_IO_PA_11, 1);
tls_spifls_di_switch(WM_IO_PA_03, 1);
@@ -863,6 +876,7 @@ static void tls_fls_flush_sector(void)
tls_spifls_do_switch(WM_IO_PA_09, 0);
tls_spifls_ck_switch(WM_IO_PA_11, 0);
tls_spifls_cs_switch(WM_IO_PA_02, 0);
FLS2_UNLOCK();
}
//gsSecOffset = 0;
@@ -1042,6 +1056,7 @@ int tls_fls_chip_erase(void)
if (inner2flashsize)
{
FLS2_LOCK();
tls_spifls_cs_switch(WM_IO_PA_02, 1);
tls_spifls_ck_switch(WM_IO_PA_11, 1);
tls_spifls_di_switch(WM_IO_PA_03, 1);
@@ -1051,6 +1066,7 @@ int tls_fls_chip_erase(void)
tls_spifls_do_switch(WM_IO_PA_09, 0);
tls_spifls_ck_switch(WM_IO_PA_11, 0);
tls_spifls_cs_switch(WM_IO_PA_02, 0);
FLS2_UNLOCK();
}
tls_mem_free(cache);
@@ -1157,6 +1173,8 @@ int tls_fls_init(void)
TLS_DBGPRT_ERR("create semaphore @fls_lock fail!\n");
return TLS_FLS_STATUS_ENOMEM;
}
tls_os_sem_create(&s_fls2_lock, 1);
inside_fls = fls;
inner1flashsize = getFlashDensity();