Michael Sauer
1b0501179d
Docker-Build mit gcc-arm-none-eabi 4.9-2014q4 (statt Homebrew-Cask) verwendet, Dockerfile/tools/docker.sh dafür aus Task 13 vorgezogen. cmake/sdk.cmake schont gcc 4.9 (kennt -fcommon/-Wno-error=... nicht). Zwei zusätzliche SDK-Stubs (EarlyInit, pre_gpio_config) in src/sys/sdk_stubs.c ergänzt, siehe sdk/PATCHES.md.
518 lines
12 KiB
C
518 lines
12 KiB
C
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/*****************************************************************************
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*
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* File Name : wm_adc.c
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*
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* Description: adc Driver Module
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*
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* Copyright (c) 2014 Winner Microelectronics Co., Ltd.
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* All rights reserved.
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*
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* Author : dave
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*
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* Date : 2014-8-15
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*****************************************************************************/
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "wm_regs.h"
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#include "wm_adc.h"
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#include "wm_dma.h"
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#include "misc.h"
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#include "wm_io.h"
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#include "wm_irq.h"
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static u16 adc_offset = 0;
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volatile ST_ADC gst_adc;
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volatile u8 adc_irq_flag = 0;
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void ADC_IRQHandler(void)
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{
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u16 adcvalue;
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int reg;
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reg = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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if(reg & CONFIG_ADC_INT) //ADC�ж�
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{
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adc_irq_flag = 1;
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tls_adc_clear_irq(ADC_INT_TYPE_ADC);
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adcvalue = tls_read_adc_result();
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if(gst_adc.adc_cb)
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gst_adc.adc_cb(&adcvalue,1);
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}
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if(reg & CONFIG_ADC_INT_CMP)
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{
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tls_adc_clear_irq(ADC_INT_TYPE_ADC_COMP);
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if(gst_adc.adc_bigger_cb)
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gst_adc.adc_bigger_cb(NULL, 0);
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}
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}
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static void adc_dma_isr_callbk(void)
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{
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if(gst_adc.adc_dma_cb)
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gst_adc.adc_dma_cb((u16 *)(ADC_DEST_BUFFER_DMA), gst_adc.valuelen);
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}
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void tls_adc_init(u8 ifusedma,u8 dmachannel)
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{
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, 0x0);
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tls_irq_enable(ADC_IRQn);
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//ע���жϺ�channel�йأ�������Ҫ������
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if(ifusedma)
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{
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gst_adc.dmachannel = tls_dma_request(dmachannel, 0); //����dma����Ҫֱ��ָ������Ϊ�����dma���ܻᱻ�������ʹ��
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tls_dma_irq_register(gst_adc.dmachannel, (void(*)(void*))adc_dma_isr_callbk, NULL, TLS_DMA_IRQ_TRANSFER_DONE);
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}
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//printf("\ndma channel = %d\n",gst_adc.dmachannel);
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}
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void tls_adc_clear_irq(int inttype)
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{
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int reg;
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reg = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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if(ADC_INT_TYPE_ADC == inttype)
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{
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reg |= CONFIG_ADC_INT;
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, reg);
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}
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else if(ADC_INT_TYPE_ADC_COMP== inttype)
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{
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reg |= CONFIG_ADC_INT_CMP;
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, reg);
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}
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else if(ADC_INT_TYPE_DMA == inttype)
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{
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tls_dma_irq_clr(gst_adc.dmachannel, TLS_DMA_IRQ_TRANSFER_DONE);
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}
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}
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void tls_adc_irq_register(int inttype, void (*callback)(u16 *buf, u16 len))
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{
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if(ADC_INT_TYPE_ADC == inttype)
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{
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gst_adc.adc_cb = callback;
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}
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else if(ADC_INT_TYPE_DMA == inttype)
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{
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gst_adc.adc_dma_cb = callback;
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}
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else if(ADC_INT_TYPE_ADC_COMP == inttype)
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{
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gst_adc.adc_bigger_cb = callback;
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}
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}
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u16 tls_read_adc_result(void)
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{
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u32 value;
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u16 ret;
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value = tls_reg_read32(HR_SD_ADC_RESULT_REG);
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ret = value&0x3fff;
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return ret;
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}
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void tls_adc_start_with_cpu(int Channel)
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{
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u32 value;
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Channel &= CONFIG_ADC_CHL_MASK;
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/* Stop adc first */
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value &= ~CONFIG_ADC_DMA_MASK;
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value &= ~CONFIG_ADC_START;
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value |= Channel;
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value |= CONFIG_ADC_START;
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value |= CONFIG_ADC_INT_MASK;
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if(Channel < 8)
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{
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value |= CONFIG_ADC_G_CTRL12;
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value &= ~ CONFIG_ADC_VCM(0x3F);
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value |= CONFIG_ADC_VCM(0x1F);
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}
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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}
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void tls_adc_enable_calibration_buffer_offset(void)
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{
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u32 value;
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/* Stop adc first */
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value &= ~CONFIG_ADC_DMA_MASK;
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value &= ~CONFIG_ADC_START;
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value |= CONFIG_ADC_CHL_OFFSET;
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value |= CONFIG_ADC_START;
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value |= CONFIG_ADC_INT_MASK;
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value |= CONFIG_ADC_EN_CAL;
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value |= CONFIG_ADC_G_CTRL12;
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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}
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void tls_adc_temp_offset_with_cpu(u8 calTemp12)
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{
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u32 value;
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value &= ~CONFIG_ADC_DMA_MASK;
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value &= ~CONFIG_ADC_START;
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value |= CONFIG_ADC_CHL_TEMP;
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value |= CONFIG_ADC_START;
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value |= CONFIG_ADC_INT_MASK;
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if(calTemp12)
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{
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value |= CONFIG_ADC_CAL_OFFSET_TEMP12;
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}
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else
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{
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value &= ~CONFIG_ADC_CAL_OFFSET_TEMP12;
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}
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value &= ~CONFIG_ADC_G_CTRL12;
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value |= CONFIG_ADC_TEMP_ON;
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value |= CONFIG_ADC_G_TEMP12(3);
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); /*start adc*/
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}
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void tls_adc_voltage_start_with_cpu(void)
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{
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u32 value;
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value &= ~CONFIG_ADC_DMA_MASK;
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value &= ~CONFIG_ADC_START;
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value |= CONFIG_ADC_CHL_VOLT;
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value |= CONFIG_ADC_START;
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value |= CONFIG_ADC_INT_MASK;
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value |= CONFIG_ADC_G_CTRL12;
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); /*start adc*/
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}
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void tls_adc_start_with_dma(int Channel, int Length)
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{
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u32 value;
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int len;
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if(Channel < 0 || Channel > 11)
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return;
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if(Length > ADC_DEST_BUFFER_SIZE)
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len = ADC_DEST_BUFFER_SIZE;
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else
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len = Length;
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gst_adc.valuelen = len;
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Channel &= CONFIG_ADC_CHL_MASK;
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value &= ~CONFIG_ADC_START; //stop
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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/* Stop dma if necessary */
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while(DMA_CHNLCTRL_REG(gst_adc.dmachannel) & 1)
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{
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DMA_CHNLCTRL_REG(gst_adc.dmachannel) = 2;
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}
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DMA_SRCADDR_REG(gst_adc.dmachannel) = HR_SD_ADC_RESULT_REG;
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DMA_DESTADDR_REG(gst_adc.dmachannel) = ADC_DEST_BUFFER_DMA;
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/* Hard, Normal, adc_req */
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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if (Channel == 8){
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DMA_MODE_REG(gst_adc.dmachannel) = (0x01 | (0+6)<<2);
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value |= (0x1 << 11);
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}
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else if (Channel == 9){
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DMA_MODE_REG(gst_adc.dmachannel) = (0x01 | (2+6)<<2);
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value |= (0x1 << 13);
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}
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else if (Channel == 10){
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DMA_MODE_REG(gst_adc.dmachannel) = (0x01 | (4+6)<<2);
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value |= (0x1 << 15);
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}
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else if (Channel == 11){
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DMA_MODE_REG(gst_adc.dmachannel) = (0x01 | (6+6)<<2);
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value |= (0x1 << 17);
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}
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else{
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DMA_MODE_REG(gst_adc.dmachannel) = (0x01 | (Channel+6)<<2);
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value |= (0x1 << (11 + Channel));
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}
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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/* Dest_add_inc, halfword, */
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DMA_CTRL_REG(gst_adc.dmachannel) = (1<<3)|(1<<5)|((len*2)<<8);
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DMA_INTMASK_REG &= ~(0x01 << (gst_adc.dmachannel *2 + 1));
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DMA_CHNLCTRL_REG(gst_adc.dmachannel) = 1; /* Enable dma */
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value |= CONFIG_ADC_START;
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value |= Channel;
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if(Channel < 8)
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{
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value |= CONFIG_ADC_G_CTRL12;
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value &= ~ CONFIG_ADC_VCM(0x3F);
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value |= CONFIG_ADC_VCM(0x1F);
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}
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// printf("config value==%x\n", value);
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); /*start adc*/
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}
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void tls_adc_stop(int ifusedma)
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{
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u32 value;
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value &= ~CONFIG_ADC_START;
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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if(ifusedma)
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tls_dma_free(gst_adc.dmachannel);
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}
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void tls_adc_config_cmp_reg(int cmp_data, int cmp_pol)
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{
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u32 value;
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cmp_data &= 0x3FFF;
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value = tls_reg_read32(HR_SD_ADC_RESULT_REG);
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value &= ~(0x3FFF<<14);
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value |= (cmp_data<<14);
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tls_reg_write32(HR_SD_ADC_RESULT_REG, value);
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value |= CONFIG_ADC_CMP_INT_MASK;
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if(cmp_pol)
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{
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value |= CONFIG_ADC_CMP_POL;
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}
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else
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{
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value &= ~CONFIG_ADC_CMP_POL;
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}
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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}
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void tls_adc_cmp_start(int Channel, int cmp_data, int cmp_pol)
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{
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u32 value;
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Channel &= CONFIG_ADC_CHL_MASK;
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/* Stop adc first */
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value &= ~CONFIG_ADC_DMA_MASK;
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value &= ~CONFIG_ADC_START;
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value |= Channel;
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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tls_adc_config_cmp_reg(cmp_data, cmp_pol);
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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value |= CONFIG_ADC_START;
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if(Channel < 8)
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{
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value |= CONFIG_ADC_G_CTRL12;
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value &= ~ CONFIG_ADC_VCM(0x3F);
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value |= CONFIG_ADC_VCM(0x1F);
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}
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); /*start adc*/
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}
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void tls_adc_reference_sel(int ref)
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{
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u32 value;
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value = tls_reg_read32(HR_SD_ADC_CONFIG_REG);
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if(ADC_REFERENCE_EXTERNAL == ref)
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{
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value &= ~CONFIG_ADC_REF_SEL;
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value |= CONFIG_ADC_BUF_BYPASS;
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}
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else if(ADC_REFERENCE_INTERNAL == ref)
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{
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value |= CONFIG_ADC_REF_SEL;
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value &= ~CONFIG_ADC_BUF_BYPASS;
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}
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tls_reg_write32(HR_SD_ADC_CONFIG_REG, value);
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}
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void tls_adc_set_clk(int div)
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{
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u32 value;
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value = tls_reg_read32(HR_CLK_DIV_CTL);
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value &= ~(0xffff<<12);
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value |= (div << 12);
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value |= ((u32)0x1<<31);
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tls_reg_write32(HR_CLK_DIV_CTL, value);
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}
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void signedToUnsignedData(u16 *adcValue, u16 *offset)
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{
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// s16 temp = 0;
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if(*adcValue >= 8192)
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{
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*adcValue -= 8192;
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}
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else
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{
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*adcValue += 8192;
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}
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/* if (*offset >=8192)
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{
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temp =((*offset-1)&0x1FFF) - 8192;
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}else{
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temp = *offset;
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}
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*adcValue -= temp;
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*/
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}
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static void waitForAdcDone(void)
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{
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while(1)
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{
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if(adc_irq_flag) //ADC�ж�
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{
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adc_irq_flag = 0;
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break;
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}
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}
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}
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static void waitForStable(void)
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{
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volatile u32 count;
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count = 2000;
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while( count-- );
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}
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u16 adc_get_offset(void)
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{
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tls_adc_init(0, 0);
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tls_adc_reference_sel(ADC_REFERENCE_INTERNAL);
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adc_irq_flag = 0;
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waitForStable();
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tls_adc_enable_calibration_buffer_offset(); //ʹ��У����
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waitForAdcDone();
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adc_offset = tls_read_adc_result(); //��ȡadcת�����
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tls_adc_stop(0);
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//printf("\r\noffset:%d", adc_offset);
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return adc_offset;
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}
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u32 adc_get_interTemp(void)
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{
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u16 code2, code1, realCode;
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u32 tem;
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tls_adc_init(0, 0);
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tls_adc_reference_sel(ADC_REFERENCE_INTERNAL);
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adc_irq_flag = 0;
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waitForStable();
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tls_adc_temp_offset_with_cpu(1); //code2
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waitForAdcDone();
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code2 = tls_read_adc_result();
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tls_adc_stop(0);
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signedToUnsignedData(&code2, &adc_offset);
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adc_irq_flag = 0;
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waitForStable();
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tls_adc_temp_offset_with_cpu(0); //code1
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waitForAdcDone();
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code1 = tls_read_adc_result();
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tls_adc_stop(0);
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signedToUnsignedData(&code1, &adc_offset);
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realCode = ( (code1-code2)/2+8192 );
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//printf("code1:%d, code2:%d, realCode:%d\r\n", code1, code2, realCode);
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//printf("\r\nTEMP:%.1f", realCode*0.12376-1294.58);
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//return (realCode*0.12376-1294.58);
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tem = realCode*124-1294580;
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//printf("tem:%d\r\n", tem);
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return tem;
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}
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u16 adc_get_inputVolt(u8 channel)
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{
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u16 average = 0;
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/*calibration*/
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adc_get_offset();
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/*get value*/
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tls_adc_init(0, 0);
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tls_adc_reference_sel(ADC_REFERENCE_INTERNAL);
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adc_irq_flag = 0;
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waitForStable();
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tls_adc_start_with_cpu(channel);
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waitForAdcDone();
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average = tls_read_adc_result();
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tls_adc_stop(0);
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signedToUnsignedData(&average, &adc_offset);
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//printf("ch[%d]inputVolt:%.3f\r\n", channel+1, ((average-8192.0)/8192*2.25/1.2 + 1.584));
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return average;
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}
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u16 adc_get_interVolt(void)
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{
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u16 voltValue;
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/*calibration*/
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adc_get_offset();
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/*get value*/
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tls_adc_init(0, 0);
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tls_adc_reference_sel(ADC_REFERENCE_INTERNAL);
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adc_irq_flag = 0;
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waitForStable();
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tls_adc_voltage_start_with_cpu();
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waitForAdcDone();
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voltValue = tls_read_adc_result();
|
||
tls_adc_stop(0);
|
||
|
||
signedToUnsignedData(&voltValue, &adc_offset);
|
||
float voltage = ( 1.214 - ((float)voltValue-8192)/8192*2.25/1.2 )*2;
|
||
printf("interVolt:%.2f\r\n", voltage);
|
||
return voltValue;
|
||
}
|
||
|
||
u32 adc_temp(void)
|
||
{
|
||
u32 tem;
|
||
adc_get_offset();
|
||
tem = adc_get_interTemp();
|
||
return tem;
|
||
}
|
||
|
||
|
||
|