Michael Sauer
1b0501179d
Docker-Build mit gcc-arm-none-eabi 4.9-2014q4 (statt Homebrew-Cask) verwendet, Dockerfile/tools/docker.sh dafür aus Task 13 vorgezogen. cmake/sdk.cmake schont gcc 4.9 (kennt -fcommon/-Wno-error=... nicht). Zwei zusätzliche SDK-Stubs (EarlyInit, pre_gpio_config) in src/sys/sdk_stubs.c ergänzt, siehe sdk/PATCHES.md.
87 lines
1.6 KiB
C
87 lines
1.6 KiB
C
/**
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* @file wm_cpu.c
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*
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* @brief cpu driver module
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*
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* @author kevin
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*
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* Copyright (c) 2014 Winner Microelectronics Co., Ltd.
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*/
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#include "wm_debug.h"
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#include "wm_regs.h"
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#include "wm_irq.h"
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#include "wm_cpu.h"
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#include "wm_pwm.h"
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#include "wm_uart.h"
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#include "wm_wifi.h"
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extern void Debug_UartInit(void);
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void tls_sys_clock_switch_hook(void)
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{
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tls_sys_clk sysclk;
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tls_sys_clk_get(&sysclk);
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tls_reg_write32(HR_TIMER_CFG, sysclk.apbclk-1);
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/*to do, like uart baudrate switch, other device clock switch*/
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tls_uart_set_baud_rate(0, 115200);
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}
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/**
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* @brief This function is used to set cpu clock
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*
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* @param[in] clk select cpu clock
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* clk == CPU_CLK_80M 80M
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* clk == CPU_CLK_40M 40M
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*
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* @return None
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*
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* @note None
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*/
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void tls_sys_clk_set(u32 clk)
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{
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u32 RegValue;
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u8 wlanDiv, cpuDiv;
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RegValue = tls_reg_read32(HR_CLK_DIV_CTL);
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wlanDiv = (RegValue>>4)&0x0F;
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RegValue &= 0xFFFFF000;
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RegValue |= 0x80000000;
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switch(clk)
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{
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case CPU_CLK_40M:
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cpuDiv = 4;
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break;
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default:
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cpuDiv = 2;
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break;
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}
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RegValue |= ((wlanDiv*4/cpuDiv)<<8) | (wlanDiv<<4) | cpuDiv;
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tls_reg_write32(HR_CLK_DIV_CTL, RegValue);
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return;
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}
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/**
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* @brief This function is used to get cpu clock
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*
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* @param[out] *sysclk point to the addr for system clk output
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*
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* @return None
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*
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* @note None
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*/
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void tls_sys_clk_get(tls_sys_clk *sysclk)
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{
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u32 value;
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value = tls_reg_read32(HR_CLK_DIV_CTL);
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sysclk->apbclk = W600_PLL_CLK_MHZ/4/((value>>4)&0x0F);
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sysclk->cpuclk = W600_PLL_CLK_MHZ/(value&0x0F);
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sysclk->wlanclk = W600_PLL_CLK_MHZ/((value>>4)&0x0F);
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}
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