95 lines
2.8 KiB
C
95 lines
2.8 KiB
C
#include <string.h>
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#include "wm_include.h"
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#include "wm_gpio_afsel.h"
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#include "drivers/nl_led.h"
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static const nl_board_t *s_board;
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static bool s_on_pwm[NL_CH_COUNT]; /* pin currently routed to the PWM unit */
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static uint8_t s_last[NL_CH_COUNT];
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static bool s_have_last;
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static void route_to_pwm(int8_t ch, uint8_t pin)
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{
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enum tls_io_name io = (enum tls_io_name)pin;
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switch (ch) {
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case 0: wm_pwm1_config(io); break;
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case 1: wm_pwm2_config(io); break;
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case 2: wm_pwm3_config(io); break;
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case 3: wm_pwm4_config(io); break;
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case 4: wm_pwm5_config(io); break;
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default: break;
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}
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}
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static void drive_gpio(const nl_pwm_chan_t *c, bool led_on)
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{
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bool level = c->active_low ? !led_on : led_on;
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tls_gpio_cfg((enum tls_io_name)c->pin, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING);
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tls_gpio_write((enum tls_io_name)c->pin, level ? 1 : 0);
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}
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void nl_pwm_leds_init(const nl_board_t *board)
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{
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s_board = board;
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s_have_last = false;
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for (int i = 0; i < NL_CH_COUNT; i++) {
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const nl_pwm_chan_t *c = &board->pwm[i];
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s_on_pwm[i] = false;
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if (c->pwm_ch < 0)
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continue;
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if (c->antiphase)
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tls_pwm_ineverse_init((u8)c->pwm_ch, board->pwm_freq_hz, 128, 0);
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else
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tls_pwm_init((u8)c->pwm_ch, board->pwm_freq_hz, 128, 0);
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tls_pwm_start((u8)c->pwm_ch);
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drive_gpio(c, false); /* dark until the engine sets a value */
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}
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}
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void nl_pwm_leds_set(const uint8_t ch[NL_CH_COUNT])
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{
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u32 cpu_sr;
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uint32_t cmp, ch4;
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if (s_have_last && memcmp(ch, s_last, NL_CH_COUNT) == 0)
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return;
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memcpy(s_last, ch, NL_CH_COUNT);
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s_have_last = true;
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/* 1. update all duty cycles at once */
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cpu_sr = tls_os_set_critical();
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cmp = tls_reg_read32(HR_PWM_CMPDAT);
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ch4 = tls_reg_read32(HR_PWM_CH4_REG2);
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for (int i = 0; i < NL_CH_COUNT; i++) {
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const nl_pwm_chan_t *c = &s_board->pwm[i];
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uint8_t v = ch[i], duty;
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if (c->pwm_ch < 0 || v == 0 || v == 255)
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continue;
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duty = (c->active_low != c->antiphase) ? (uint8_t)(255 - v) : v;
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if (c->pwm_ch == 4)
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ch4 = (ch4 & ~0x0000FF00u) | ((uint32_t)duty << 8);
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else
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cmp = (cmp & ~(0xFFu << (c->pwm_ch * 8))) | ((uint32_t)duty << (c->pwm_ch * 8));
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}
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tls_reg_write32(HR_PWM_CMPDAT, cmp);
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tls_reg_write32(HR_PWM_CH4_REG2, ch4);
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tls_os_release_critical(cpu_sr);
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/* 2. switch pins between GPIO (0 / 255) and PWM */
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for (int i = 0; i < NL_CH_COUNT; i++) {
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const nl_pwm_chan_t *c = &s_board->pwm[i];
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uint8_t v = ch[i];
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if (c->pwm_ch < 0)
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continue;
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if (v == 0 || v == 255) {
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drive_gpio(c, v == 255);
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s_on_pwm[i] = false;
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} else if (!s_on_pwm[i]) {
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route_to_pwm(c->pwm_ch, c->pin);
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s_on_pwm[i] = true;
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}
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}
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}
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