Michael Sauer
1b0501179d
Docker-Build mit gcc-arm-none-eabi 4.9-2014q4 (statt Homebrew-Cask) verwendet, Dockerfile/tools/docker.sh dafür aus Task 13 vorgezogen. cmake/sdk.cmake schont gcc 4.9 (kennt -fcommon/-Wno-error=... nicht). Zwei zusätzliche SDK-Stubs (EarlyInit, pre_gpio_config) in src/sys/sdk_stubs.c ergänzt, siehe sdk/PATCHES.md.
582 lines
20 KiB
C
582 lines
20 KiB
C
/**************************************************************************//**
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* @file wm_i2s.h
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* @author
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* @version
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* @date
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* @brief
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*
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* @copyright (c) 2014 Winner Microelectronics Co., Ltd. All rights reserved.
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*****************************************************************************/
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#ifndef __WM_I2S_H
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#define __WM_I2S_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "wm_type_def.h"
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#include "wm_regs.h"
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#include "wm_osal.h"
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#include "misc.h"
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#include "wm_dma.h"
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#define I2S_CTRL_FORMAT_Pos (24) /*!< CTRL : FORMAT Position */
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#define I2S_CTRL_FORMAT_MASK (3UL<<I2S_CTRL_FORMAT_Pos) /*!< CTRL : FORMAT mask */
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#define I2S_CTRL_FORMAT_I2S (0x0UL<<I2S_CTRL_FORMAT_Pos) /*!< I2S data format*/
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#define I2S_CTRL_FORMAT_MSB (0x1UL<<I2S_CTRL_FORMAT_Pos) /*!< MSB data format*/
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#define I2S_CTRL_FORMAT_PCMA (0x2UL<<I2S_CTRL_FORMAT_Pos) /*!< PCMA data format*/
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#define I2S_CTRL_FORMAT_PCMB (0x3UL<<I2S_CTRL_FORMAT_Pos) /*!< PCMB data format*/
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#define I2S_CTRL_DATABIT_MASK (0x30UL) /*!< CTRL : DATABIT mask */
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#define I2S_CTRL_DATABIT_8 ((uint8_t)0x0) /*!< I2S data width is 8-bit */
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#define I2S_CTRL_DATABIT_16 ((uint8_t)0x10) /*!< I2S data width is 16-bit */
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#define I2S_CTRL_DATABIT_24 ((uint8_t)0x20) /*!< I2S data width is 24-bit */
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#define I2S_CTRL_DATABIT_32 ((uint8_t)0x30) /*!< I2S data width is 32-bit */
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#define I2S_CTRL_CHSEL_Pos (23) /*!< CTRL : Channel select position */
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#define I2S_CTRL_CHSEL_MASK (1UL<<I2S_CTRL_CHSEL_Pos) /*!< CTRL: Channel select mask */
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#define I2S_CTRL_CHSEL_LEFT (1UL<<I2S_CTRL_CHSEL_Pos) /*!< CTRL: Left channel select */
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#define I2S_CTRL_CHSEL_RIGHT (0UL<<I2S_CTRL_CHSEL_Pos) /*!< CTRL: Right channel select */
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#define I2S_CTRL_STEREO_MONO_Pos (22) /*!< CTRL: STEREO MONO Position */
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#define I2S_CTRL_STEREO_MONO_MASK (1UL<<I2S_CTRL_STEREO_MONO_Pos) /*!< CTRL: STEREO MONO MASK */
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#define I2S_CTRL_MONO (1UL<<I2S_CTRL_STEREO_MONO_Pos) /*!< Monaural channel */
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#define I2S_CTRL_STERO (0UL<<I2S_CTRL_STEREO_MONO_Pos) /*!< Stereo channel */
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#define I2S_CTRL_RXDMA_Pos (21) /*!< CTRL: RXDMA Position */
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#define I2S_CTRL_RXDMA_MASK (1UL<<I2S_CTRL_RXDMA_Pos) /*!< CTRL: RXDMA mask */
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#define I2S_CTRL_TXDMA_Pos (20) /*!< CTRL: TXDMA Position*/
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#define I2S_CTRL_TXDMA_MASK (1UL<<I2S_CTRL_TXDMA_Pos) /*!< CTRL: TXDMA mask */
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#define I2S_CTRL_RX_CLR_Pos (19) /*!< CTRL: RXFIFO clear Position */
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#define I2S_CTRL_RX_CLR_MASK (1UL<<I2S_CTRL_RX_CLR_Pos) /*!< CTRL: RXFIFO clear mask */
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#define I2S_CTRL_TX_CLR_Pos (18) /*!< CTRL: TXFIFO clear Position */
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#define I2S_CTRL_TX_CLR_MASK (1UL<<I2S_CTRL_TX_CLR_Pos) /*!< CTRL: TXFIFO clear mask */
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#define I2S_CTRL_LZCEN_Pos (17) /*!< CTRL: LZCEN Position */
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#define I2S_CTRL_LZCEN_MASK (1UL<<I2S_CTRL_LZCEN_Pos) /*!< CTRL: LZCEN mask */
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#define I2S_CTRL_RZCEN_Pos (16) /*!< CTRL: RZCEN Position */
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#define I2S_CTRL_RZCEN_MASK (1UL<<I2S_CTRL_RZCEN_Pos) /*!< CTRL: RZCEN mask */
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#define I2S_CTRL_RXTH_Pos (12) /*!< CTRL: RXTH Position */
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#define I2S_CTRL_RXTH_MASK (7UL<<I2S_CTRL_RXTH_Pos) /*!< CTRL: RXTH mask */
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#define I2S_CTRL_TXTH_Pos (9) /*!< CTRL: TXTH Position */
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#define I2S_CTRL_TXTH_MASK (7UL<<I2S_CTRL_TXTH_Pos) /*!< CTRL: TXTH mask */
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#define I2S_CTRL_MUTE_Pos (3) /*!< CTRL: MUTE Position */
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#define I2S_CTRL_MUTE_MASK (1UL<<I2S_CTRL_MUTE_Pos) /*!< CTRL: MUTE mask */
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#define I2S_CTRL_RXE_Pos (2) /*!< CTRL: RXEN Position */
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#define I2S_CTRL_RXE_MASK (1UL<<I2S_CTRL_RXE_Pos) /*!< CTRL: RXEN mask */
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#define I2S_CTRL_TXE_Pos (1) /*!< CTRL: TXEN Position */
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#define I2S_CTRL_TXE_MASK (1UL<<I2S_CTRL_TXE_Pos) /*!< CTRL: TXEN mask */
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#define I2S_CTRL_EN_Pos (0) /*!< CTRL: EN Position */
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#define I2S_CTRL_EN_MASK (1UL<<I2S_CTRL_EN_Pos) /*!< CTRL: EN mask */
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#define I2S_INT_MASK_LZC ((uint16_t)0x200) /*!< Left Channel Zero-Cross Interrupt MASK */
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#define I2S_INT_MASK_RZC ((uint16_t)0x100) /*!< Right Channel Zero-Cross Interrupt MASK */
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#define I2S_INT_MASK_TXDONE ((uint16_t)0x080) /*!< Transmit Done Interrupt Mask */
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#define I2S_INT_MASK_TXTH ((uint16_t)0x040) /*!< Transmit FIFO Threshold level Interrupt MASK */
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#define I2S_INT_MASK_TXOV ((uint16_t)0x020) /*!< Transmit FIFO Overflow Interrupt MASK */
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#define I2S_INT_MASK_TXUD ((uint16_t)0x010) /*!< Transmit FIFO Underflow Interrupt MASK */
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#define I2S_INT_MASK_RXDONE ((uint16_t)0x008) /*!< Receive Done Interrupt Mask */
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#define I2S_INT_MASK_RXTH ((uint16_t)0x004) /*!< Receive FIFO Threshold level Interrupt MASK */
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#define I2S_INT_MASK_RXOV ((uint16_t)0x002) /*!< Receive FIFO Overflow Interrupt MASK */
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#define I2S_INT_MASK_RXUD ((uint16_t)0x001) /*!< Receive FIFO Underflow Interrupt MASK */
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#define I2S_FLAG_TX_Pos (12) /*!< INT_SRC: TX interrupt flag Position */
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#define I2S_FLAG_RX_Pos (11) /*!< INT_SRC: RX interrupt flag Position */
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#define I2S_FLAG_I2S_Pos (10) /*!< INT_SRC: I2S module interrupt flag Position */
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#define I2S_FLAG_LZC_Pos (9) /*!< INT_SRC: LZC module interrupt flag Position */
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#define I2S_FLAG_RZC_Pos (8) /*!< INT_SRC: RZC module interrupt flag Position */
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#define I2S_FLAG_TXDONE_Pos (7) /*!< INT_SRC: TXDONE module interrupt flag Position */
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#define I2S_FLAG_TXTH_Pos (6) /*!< INT_SRC: TXTH module interrupt flag Position */
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#define I2S_FLAG_TXOV_Pos (5) /*!< INT_SRC: TXOV module interrupt flag Position */
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#define I2S_FLAG_TXUD_Pos (4) /*!< INT_SRC: TXUD module interrupt flag Position */
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#define I2S_FLAG_RXDONE_Pos (3) /*!< INT_SRC: RXDONE module interrupt flag Position */
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#define I2S_FLAG_RXTH_Pos (2) /*!< INT_SRC: RXTH module interrupt flag Position */
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#define I2S_FLAG_RXOV_Pos (1) /*!< INT_SRC: RXOV module interrupt flag Position */
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#define I2S_FLAG_RXUD_Pos (0) /*!< INT_SRC: RXUD module interrupt flag Position */
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#define I2S_FLAG_TX (1<<I2S_FLAG_TX_Pos) /*!< INT_SRC: TX interrupt flag */
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#define I2S_FLAG_RX (1<<I2S_FLAG_RX_Pos) /*!< INT_SRC: RX interrupt flag */
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#define I2S_FLAG_I2S (1<<I2S_FLAG_I2S_Pos) /*!< INT_SRC: I2S module interrupt flag */
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#define I2S_FLAG_LZC (1<<I2S_FLAG_LZC_Pos) /*!< INT_SRC: LZC module interrupt flag */
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#define I2S_FLAG_RZC (1<<I2S_FLAG_RZC_Pos) /*!< INT_SRC: RZC module interrupt flag */
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#define I2S_FLAG_TXDONE (1<<I2S_FLAG_TXDONE_Pos) /*!< INT_SRC: TXDONE module interrupt flag */
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#define I2S_FLAG_TXTH (1<<I2S_FLAG_TXTH_Pos) /*!< INT_SRC: TXTH module interrupt flag */
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#define I2S_FLAG_TXOV (1<<I2S_FLAG_TXOV_Pos) /*!< INT_SRC: TXOV module interrupt flag */
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#define I2S_FLAG_TXUD (1<<I2S_FLAG_TXUD_Pos) /*!< INT_SRC: TXUD module interrupt flag */
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#define I2S_FLAG_RXDONE (1<<I2S_FLAG_RXDONE_Pos) /*!< INT_SRC: RXDONE module interrupt flag */
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#define I2S_FLAG_RXTH (1<<I2S_FLAG_RXTH_Pos) /*!< INT_SRC: RXTH module interrupt flag */
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#define I2S_FLAG_RXOV (1<<I2S_FLAG_RXOV_Pos) /*!< INT_SRC: RXOV module interrupt flag */
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#define I2S_FLAG_RXUD (1<<I2S_FLAG_RXUD_Pos) /*!< INT_SRC: RXUD module interrupt flag */
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#define I2S_RX_FIFO_CNT_MASK (0x0F) /*!< RX fifo count mask */
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#define I2S_TX_FIFO_CNT_MASK (0xF0) /*!< TX fifo count mask */
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#define I2S_MAX_RXTXFIFO_LEVEL (8) /*!< max rx/tx fifo level */
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#define WM_I2S_TX_DMA_CHANNEL (4)
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#define WM_I2S_RX_DMA_CHANNEL (5)
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typedef void (*tls_i2s_callback)();
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typedef struct
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{
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/** I2S Control Register */
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__IO uint32_t CTRL;
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/** I2S Interrupt mask Register */
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__IO uint32_t INT_MASK;
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/** I2S Interrupt source Register */
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__IO uint32_t INT_SRC;
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/** I2S Interrupt status Register */
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__I uint32_t INT_STATUS;
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/** I2S TX data Register */
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__O uint32_t TX;
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/** I2S RX data Register */
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__I uint32_t RX;
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} I2S_T;
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/** base address of the I2S module */
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#define I2S ((I2S_T *)HR_I2S_REG_BASE)
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typedef enum
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{
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/** left channel select */
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I2S_CHANNEL_LEFT = I2S_CTRL_CHSEL_LEFT,
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/** right channel select */
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I2S_CHANNEL_RIGHT = I2S_CTRL_CHSEL_RIGHT
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} I2S_CHANNEL_SEL;
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typedef struct tls_i2s_options
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{
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/** I2S receiver enable */
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uint8_t rx_en;
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/** I2S transfer enable */
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uint8_t tx_en;
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/** I2S Stereo or Monaural
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- \ref I2S_CTRL_STERO
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- \ref I2S_CTRL_MONO
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*/
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uint32_t stereo_mono;
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/** I2S module format
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- \ref I2S_CTRL_FORMAT_I2S
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- \ref I2S_CTRL_FORMAT_MSB
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- \ref I2S_CTRL_FORMAT_PCMA
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- \ref I2S_CTRL_FORMAT_PCMB
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*/
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uint32_t format;
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/** I2S module data width
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- \ref I2S_CTRL_DATABIT_8
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- \ref I2S_CTRL_DATABIT_16
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- \ref I2S_CTRL_DATABIT_24
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- \ref I2S_CTRL_DATABIT_32
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*/
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uint32_t data_width;
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/** I2S module sample rate max 128KHz */
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uint32_t sample_rate;
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} tls_i2s_options_t;
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typedef struct tls_i2s_buf_t
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{
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/** pointer the bufffer address */
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uint32_t * buf;
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/** the buffer size in bytes */
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uint16_t len;
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/** current position of the data */
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uint16_t index;
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}tls_i2s_buf;
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typedef struct _tls_i2s_port
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{
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/** i2s config params */
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struct tls_i2s_options opts;
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/** pointer to the I2S registers */
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I2S_T * regs;
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/** the semaphore used to synchronous transmission */
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tls_os_sem_t *tx_sem;
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/** instance of tls_i2s_buf struct for data receive */
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tls_i2s_buf rx_buf;
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/** instance of tls_i2s_buf struct for data receive */
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tls_i2s_buf tx_buf;
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/** function pointer for data receiver when in interrupt mode */
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void (*rx_callback)(u16 len);
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/** function pointer for data transmit when in interrupt mode */
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void (*tx_callback)(u16 len);
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} tls_i2s_port_t;
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/**
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* @defgroup Driver_APIs Driver APIs
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* @brief Driver APIs
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*/
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/**
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* @addtogroup Driver_APIs
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* @{
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*/
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/**
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* @defgroup I2S_Driver_APIs I2S Driver APIs
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* @brief I2S driver APIs
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*/
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/**
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* @addtogroup I2S_Driver_APIs
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* @{
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*/
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/**
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* @brief This function is used to initial i2s port.
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* @param[in] opts the i2s setting options,if this param is NULL,this function will use the default options.
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* @retval
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* - \ref WM_SUCCESS
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* - \ref WM_FAILED
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*
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*/
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int tls_i2s_port_init(tls_i2s_options_t *opts);
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/**
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* @brief This function is used to config i2s port.
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* @param[in] opts is the i2s setting options
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*
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*/
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void tls_i2s_config(tls_i2s_options_t *opts);
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/**
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* @brief Set the frequency of the i2s port.
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* @param[in] freq the required frequency of the i2s module
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* @retval
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*
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*/
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void tls_i2s_set_freq(uint32_t freq);
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/**
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* @brief set the frequency of the i2s port.
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*
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* @param[in] freq the required frequency of the i2s module
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* @param[in] exclk the frequency of the external clock
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*
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* @retval
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*
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*/
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void wm_i2s_set_freq_exclk(uint32_t freq, uint32_t exclk);
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/**
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* @brief This function is used to transfer data in blocking mode.
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* @param[in] buf pointer to data buffer
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* @param[in] len amount of data to be sent.
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* @retval
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* - \ref WM_SUCCESS
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* - \ref WM_FAILED
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*/
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int tls_i2s_tx_block(uint32_t *buf, uint16_t len);
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/**
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* @brief This function is used to transfer data in non-blocking mode.
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* @param[in] buf pointer to data buffer
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* @param[in] len bytes of data to be sent.
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* @param[in] tx_callback function pointer to a callback,when the data have been sent this specified function will be called
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* @retval
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* - \ref WM_SUCCESS
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* - \ref WM_FAILED
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* @note
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* this function only submit the data
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* when the data transfer finished the tx_callback function will be called
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*/
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int tls_i2s_tx_nonblock(uint32_t *buf, uint16_t len, void (*tx_callback)(u16 len));
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/**
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* @brief This function is used to receive data in non-blocking mode.
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* @param[in] buf pointer to data buffer
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* @param[in] len bytes of data to be sent.
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* @param[in] rx_callback function pointer to a callback,when the data have been received this specified function will be called
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*
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* @retval
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* - \ref WM_SUCCESS
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* - \ref WM_FAILED
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* @note
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*
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*/
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int tls_i2s_rx_nonblock(uint32_t *buf, uint16_t len, void (*rx_callback)(u16 len));
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/**
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* @brief This function is used to transmit data in DMA mode.
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* @param[in] buf pointer to data buffer
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* @param[in] len bytes of data to be sent.
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* @param[in] callback function pointer to a callback,when the data have been sent this specified function will be called
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* @retval
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* - \ref WM_SUCCESS
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* - \ref WM_FAILED
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* @note
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*
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*/
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int tls_i2s_tx_dma(uint32_t * addr, uint16_t len, tls_i2s_callback callback);
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/**
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* @brief This function is used to receive data in DMA mode.
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* @param[in] addr pointer to data buffer
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* @param[in] len bytes of data to be sent.
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* @param[in] callback function pointer to a callback,when the data have been received this specified function will be called
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* @retval
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* - \ref WM_SUCCESS
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* - \ref WM_FAILED
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* @note
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* this function only submit the data
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* when the data transfer finished the callback function will be called
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*/
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int tls_i2s_rx_dma(uint32_t * addr, uint16_t len, tls_i2s_callback callback);
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/**
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* @brief Enable I2S module
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*
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*/
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#define TLS_I2S_ENABLE() (I2S->CTRL |= I2S_CTRL_EN_MASK)
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/**
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* @brief Disable I2S module
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*
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*/
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#define TLS_I2S_DISABLE() (I2S->CTRL &= ~I2S_CTRL_EN_MASK)
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/**
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* @brief Enable clock of I2S module
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*
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*/
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#define TLS_I2S_CLK_ENABLE() \
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do { \
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tls_bitband_write(HR_CLK_BASE_ADDR, HR_CLK_I2S_GATE_Pos , 1); \
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} while(0)
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/**
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* @brief Disnable clock of I2S module
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*
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*/
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#define TLS_I2S_CLK_DISABLE() \
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do { \
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tls_bitband_write(HR_CLK_BASE_ADDR, HR_CLK_I2S_GATE_Pos , 0); \
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} while(0)
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/**
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* @brief Enable transmit of I2S module
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*
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*/
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#define TLS_I2S_TX_ENABLE() \
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do { \
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tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_TXE_Pos, 1); \
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} while(0)
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/**
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* @brief Disable transmit of I2S module
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*
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*/
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#define TLS_I2S_TX_DISABLE() \
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do { \
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tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_TXE_Pos, 0); \
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} while(0)
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/**
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* @brief Enable receive of I2S module
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*
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*/
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#define TLS_I2S_RX_ENABLE() \
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do { \
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tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_RXE_Pos, 1); \
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} while(0)
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/**
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* @brief Disable receive of I2S module
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*
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*/
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#define TLS_I2S_RX_DISABLE() \
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do { \
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tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_RXE_Pos, 0); \
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} while(0)
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|
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/**
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* @brief Clear receive FIFO
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*
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*/
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#define TLS_I2S_RX_FIFO_CLEAR() \
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do { \
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tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_RX_CLR_Pos, 1); \
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} while(0)
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/**
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* @brief Clear transmit FIFO
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*
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*/
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#define TLS_I2S_TX_FIFO_CLEAR() \
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do { \
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tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_TX_CLR_Pos, 1); \
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} while(0)
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|
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/**
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* @brief Enable transmit DMA request
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|
*
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|
*/
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#define TLS_I2S_TXDMA_ENABLE() (I2S->CTRL |= I2S_CTRL_TXDMA_MASK)
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|
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/**
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* @brief Disnable transmit DMA request
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|
*
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|
*/
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#define TLS_I2S_TXDMA_DISABLE() (I2S->CTRL &= ~I2S_CTRL_TXDMA_MASK)
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|
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/**
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|
* @brief Enable receive DMA request
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|
*
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|
*/
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#define TLS_I2S_RXDMA_ENABLE() (I2S->CTRL |= I2S_CTRL_RXDMA_MASK)
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|
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/**
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|
* @brief Disnable receive DMA request
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|
*
|
|
*/
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|
#define TLS_I2S_RXDMA_DISABLE() (I2S->CTRL &= ~I2S_CTRL_RXDMA_MASK)
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|
|
|
/**
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|
* @brief Left channel zero-cross detection enable
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|
*
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|
*/
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|
#define TLS_I2S_LZC_ENABLE() (I2S->CTRL |= I2S_CTRL_LZCEN_MASK)
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|
|
|
/**
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|
* @brief Left channel zero-cross detection disable
|
|
*
|
|
*/
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|
#define TLS_I2S_LZC_DISABLE() (I2S->CTRL &= ~I2S_CTRL_LZCEN_MASK)
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|
|
|
/**
|
|
* @brief Right channel zero-cross detection enable
|
|
*
|
|
*/
|
|
#define TLS_I2S_RZC_ENABLE() (I2S->CTRL |= I2S_CTRL_RZCEN_MASK)
|
|
|
|
/**
|
|
* @brief Right channel zero-cross detection disable
|
|
*
|
|
*/
|
|
#define TLS_I2S_RZC_DISABLE() (I2S->CTRL &= ~I2S_CTRL_RZCEN_MASK)
|
|
|
|
/** @brief Enable transmit mute
|
|
*
|
|
*/
|
|
#define TLS_I2S_TX_MUTE_ENABLE() (I2S->CTRL |= I2S_CTRL_MUTE_MASK)
|
|
|
|
/**
|
|
* @brief Disable transmit mute
|
|
*
|
|
*/
|
|
#define TLS_I2S_TX_MUTE_DISABLE() (I2S->CTRL &= ~ I2S_CTRL_MUTE_MASK)
|
|
|
|
/**
|
|
* @brief Set receive FIFO threshold level
|
|
* @param[in] level The value set to Rx threshold level
|
|
*
|
|
*/
|
|
static __inline__ void tls_i2s_set_rxth(uint8_t level)
|
|
{
|
|
if (level > 8)
|
|
{
|
|
level = 3;
|
|
}
|
|
I2S->CTRL &= ~ I2S_CTRL_RXTH_MASK;
|
|
I2S->CTRL |= ((level - 1)<<I2S_CTRL_RXTH_Pos);
|
|
}
|
|
|
|
/**
|
|
* @brief Set transmit FIFO threshold level
|
|
* @param[in] level The value set to Tx threshold level
|
|
*/
|
|
static __inline__ void tls_i2s_set_txth(uint8_t level)
|
|
{
|
|
if (level > 8)
|
|
level = 4;
|
|
I2S->CTRL &= ~ I2S_CTRL_TXTH_MASK;
|
|
I2S->CTRL |= (level<<I2S_CTRL_TXTH_Pos);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable receiver of I2S module
|
|
* @param[in] enable When one enable the receiver of I2S module, when zero disable
|
|
*/
|
|
static __inline__ void tls_i2s_channel_sel(I2S_CHANNEL_SEL channel_sel)
|
|
{
|
|
I2S->CTRL &= ~ I2S_CTRL_CHSEL_MASK;
|
|
I2S->CTRL |= channel_sel;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the specified I2S interrupts
|
|
* @param[in] i2s_int_mask specifies the I2S interrupt sources to be enabled or disabled.
|
|
* This parameter can be one of the following values:
|
|
* - \ref I2S_INT_MASK_LZC
|
|
* - \ref I2S_INT_MASK_RZC
|
|
* - \ref I2S_INT_MASK_TXDONE
|
|
* - \ref I2S_INT_MASK_TXTH
|
|
* - \ref I2S_INT_MASK_TXOV
|
|
* - \ref I2S_INT_MASK_TXUD
|
|
* - \ref I2S_INT_MASK_RXDONE
|
|
* - \ref I2S_INT_MASK_RXTH
|
|
* - \ref I2S_INT_MASK_RXOV
|
|
* - \ref I2S_INT_MASK_RXUD
|
|
* @param[in] enable when set 1 disable interrupt, 0 enable
|
|
* @retval None
|
|
*/
|
|
static __inline__ void tls_i2s_int_config(uint32_t i2s_int_mask, uint8_t enable)
|
|
{
|
|
if(enable)
|
|
{
|
|
I2S->INT_MASK &= ~i2s_int_mask;
|
|
}
|
|
else
|
|
{
|
|
I2S->INT_MASK |= i2s_int_mask;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable master clock (MCLK).
|
|
* @param[in] clock The target MCLK clock rate.
|
|
* @retval actual MCLK clock rate
|
|
* @details Set the master clock rate according to u32BusClock parameter and enable master clock output.
|
|
* The actual master clock rate may be different from the target master clock rate.
|
|
* The real master clock rate will be returned for reference.
|
|
*/
|
|
uint32_t tls_i2s_mclk_enable(uint32_t clock);
|
|
|
|
/**
|
|
* @brief disable master clock (MCLK).
|
|
*
|
|
*/
|
|
void tls_i2s_mclk_disable(void);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /** __WM_I2S_H*/
|
|
|
|
|
|
/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/
|